For the project, assume a 16-bit memory byte address.
Part 1. Design three caches with the following organizations. The cache size for each cache is 64 bytes. The block size is 1 word (where 1 word = 4 bytes).
- Design a direct mapped cache.
- Design a two-way set associative cache. Use the LRU replacement policy.
- Design a fully associative cache. Use the LRU replacement policy.
Note: You should design your models in Part 1 so that the block size, cache size, and set associativity can be varied easily. This will simplify parts 2 – 4.
Part 2. Explore the effect of block size. For each cache organization in part 1, simulate the following block sizes.
- 1 word block (same as part 1)
- 2 word block
- 4 word block
Part 3. Explore the effect of cache size. For each cache organization in part 1, simulate the following cache sizes. Assume a 1-word block.
- 64 bytes (same as part 1)
- 128 bytes
- 256 bytes
Part 4. Explore the effect of set associativity. For a 64-byte cache and a 1-word block, consider the impact of set-associativity.
- 1-way set associativity (same as direct mapped cache in part 1).
- 2-way set associativity (same as 2-way set associative cache in part 1).
- 4-way set associativity
- 8-way set associativity
- 16-way set associativity (same as fully associative cache in part 1).
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